Integrated video equalizer and jitter cleaner

ABSTRACT

An integrated system for adaptive equalization and jitter reduction of a video signal that includes an adaptive equalizer and a jitter cleaner located on one integrated circuit within a single package. An adaptive equalizer applies frequency specific signal modification to the received signal. A bit rate detector determines a bit rate of the video signal or the equalized signal. The jitter cleaner couples to the adaptive equalizer output and processes the equalized signal to reduce jitter in the equalized signal. A multiplexer receives the equalized signal and the jitter cleaner output and, responsive to a control signal, outputs either the equalized signal or the jitter cleaner output signal. A status monitor may optionally be included to compare the detected bit rate to a bit rate threshold, and a responsive to the comparing activate or deactivate the jitter cleaner and output either the equalized signal or jitter cleaner output.

1. PRIORITY CLAIM

This application claims priority to and the benefit of U.S. ProvisionalApplication No. 61/621,933 filed Apr. 9, 2012 entitled Integrated VideoEqualizer and Jitter Cleaner.

2. FIELD OF THE INVENTION

This innovation relates to video signal processing and in particular tovideo signal equalization and jitter reduction.

3. RELATED ART

Video processing equipment is commonly used in numerous industries.Video signals representing video images typically originate at a sourceand must be sent to processing equipment or a display screen forviewing. As is understood, transmission of an electrical signal over achannel, such as coaxial cable or twisted pair cable, leads todegradation of the electrical signal. The signals typically comprisepulses, which may be converted to an analog representation. In videoapplications, this degradation is significant due to the frequencyrequired to support video applications, which may be in the gigahertzrange. Video broadcast equipment makers continue to use long reaches ofcoaxial cabling to route ever increasing speeds of serial digital datafrom a transmitter to a receiver. Losses associated with the coaxialcable (channel) have necessitated frequency dependent gain for signalrecovery (also known as equalization). For example, during transmissionhigh frequencies are typically attenuated to a larger degree than lowerfrequencies and the transfer function of the channel will thus affectthe received signal. As a result of the degradation, the recover orprocessing of the signal at the receiver may result in unacceptably highbit error rates or other unwanted signal anomalies.

To address the frequency specific signal degradation when processing ordisplaying the video image, a video equalizer at the receiver isutilized. The equalizer is configured to adjust the frequency specificattenuation of the received signal resulting from the channel.Equalization alone has been an effective tool to meet specification forlink reaches up to 30 dB loss at half the clock rate. Equalizationtechnology however does have limitations in its ability to provide areliable signal for downstream elements as channel length andfrequencies increase. This is due to imperfect matching of the channel(transmission line) and a reduction of signal to noise ratio as thevideo data gets attenuated. These non-idealities manifest as an increaseof jitter presented to downstream elements such as FPGAs.

In addition, if cross-point switches are part of the signal path, jittermay be introduced into the signal. The jitter may affect the timing,amplitude, phase, or any combination thereof. For example, at 3 Gb/s andgreater signal frequencies and for long reach channel lengths, randomjitter and deterministic jitter may be introduce into the signal.

To alleviate this additional signal degredation, system vendors haveadded a separate and discrete reclocker in their design so that a lowjitter signal could be presented to downstream signal processingcomponents. The reclocker may be utilized to recover and retime the databased on a known or derived clock signal. Though the eye of the signalmay be open, signal recovery can be difficult even with a good reclockercircuit. In addition, as the signal travels though cross-point switchesor interconnects, the signal pulses become more narrow due to jitter andeventually vanish. This results in the signal becoming non-recoverable.A jitter cleaner is used to retime the clock and retime each symbol soit can pass through band width limiting circuits. Prior art systemswould often apply a reclocker after the cross-point switch because pulseshrinkage can occur in the cross-point switch, which can limit the reachat the input side.

To overcome the drawbacks of the prior art and provide additionalbenefit, an integrated equalizer and clock data recovery circuit isdisclosed herein.

SUMMARY

To overcome the drawbacks of the prior art and provide additionalbenefits, an integrated system for adaptive equalization and jitterreduction is disclosed. In one embodiment input is configured to receivea video signal from a channel and an adaptive equalizer is configured toapply frequency specific signal modification to the received signal topresent an equalized signal on an adaptive equalizer output. Also partof this embodiment is a bit rate detector configure to determine a bitrate of the video signal or the equalized signal and a jitter cleanerhaving a jitter cleaner input coupled to the adaptive equalizer output.The jitter cleaner is configured to process the equalized signal toreduce jitter in the equalized signal to create a jitter cleaner output.Also disclosed is a multiplexer configured to receive the equalizedsignal and the jitter cleaner output and, responsive to a controlsignal, output either the equalized signal or the jitter cleaner output.A status monitor is configured to compare the detected bit rate to a bitrate threshold, and a responsive to the detected bit rate being greaterthan the bit rate threshold, activate the jitter cleaner to processesthe equalized signal and generate a control signal which causes themultiplexer to output the jitter cleaner output. Alternatively, if thedetected bit rate is greater than the bit rate threshold then activatingthe jitter cleaner to process the equalized signal and generate acontrol signal which causes the multiplexer to output the jitter cleaneroutput.

In one embodiment the system further comprises an amplifier configuredto amplify the signal prior to equalization by the adaptive equalizer.The jitter cleaner may comprise a clock and data recovery system. In oneembodiment, the threshold bit rate is 1 Gb/s. In one configuration thechannel is a coaxial cable having losses in excess of 30 dB at 1.5 GHz.The signal may include SMPTE standard data rates including 2.97 Gb/s and1.485 Gb/s, or any other SMPTE data rate. It is also contemplated that adecision feedback equalizer be located between the adaptive equalizerand the jitter cleaner such that the decision feedback equalizer isconfigured to process the equalized signal to reduce noise in theequalized signal. As such, the invention may also include a noisedetector configured to compare noise on the video signal or theequalizer output to a noise threshold and responsive to the comparing,activate or disable the decision feedback equalizer.

Also disclosed herein is a combined integrated circuit configured as anequalizer and clock/data recovery system contained within a singlepackage comprising a package configured with an inner area and two moreelectrical pins and a die located in the inner area of the package, thedie configured as an integrated circuit configured with the followingelements. Also part of this embodiment is an equalizer configure toperform equalization of a received signal to generate an equalizedsignal, a clock/data recovery system configured to retime the equalizedsignal to create a retimed signal, and a bit rate detector configured tocalculate a bit rate of the received signal. Also part of thisembodiment is a comparator configured to compare the bit rate of thereceived signal to a bit rate threshold and a control circuit configuredto selectively power down the clock/data recovery system if the bit rateof the received signal is below the bit rate threshold.

In one embodiment the die further includes a decision feedback equalizerconfigured to receive and process the equalized signal and present adecision feedback equalizer processed signal to the clock data recoverysystem. The control circuit may be further configured to power down thedecision feedback equalizer based on one or more parameters of thereceived signal. In one configuration the system further includes aswitch configured to receive the equalized signal and the retimed signaland if the clock/data recovery system is powered down, then the systemwill output the equalized signal and if the clock/data recovery systemis not powered down, then the system will output the retimed signal.This control circuit may be part of a status monitor and the statusmonitor may be is configured to process the bit rate and generate thecontrol signal. The status monitor or interface may be used to accessone or more parameters of the equalizer and clock/data recovery systemand monitor the equalized signal and retimed signal.

Also disclosed herein is a method for processing a video signal toperform noise and jitter reduction. In one embodiment this methodcomprises receiving a video signal and performing adaptive equalizationon the video signal with an adaptive equalizer to create an equalizedsignal. Then the method provides the equalized signal to a switch and aretiming circuit. The method also compares one or more aspects of theequalized signal to a threshold and responsive to the comparing, eitheroutputs the equalized signal or activates a retiming circuit to processthe equalized signal to create a retimed signal, which is presented asthe output.

In one embodiment the retime circuit comprises a clock/data recoverycircuit including a phase lock loop circuit. The method may furthercomprise performing processing with a decision feedback equalizer toreduce noise on at least one of the video signal, the equalized signal,or the retimed signal. It is contemplated that performing adaptiveequalization and processing the equalized signal to create a retimedsignal occurs in the same integrated circuit within a package. Thismethod of operation may also include generating a control signal whichis presented to a switch or multiplexer, to control which input to theswitch is output from the switch, such that the switch input includes atleast the equalized signal and the retimed signal. The adaptiveequalizer and retiming circuit may be coupled to a user interface orstatus monitor. The one or more aspects of the equalized signal may be abit rate of the equalized signal or the video signal and the bit ratedetector determines the bit rate.

Other systems, methods, features and advantages of the invention will beor will become apparent to one with skill in the art upon examination ofthe following figures and detailed description. It is intended that allsuch additional systems, methods, features and advantages be includedwithin this description, be within the scope of the invention, and beprotected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The components in the figures are not necessarily to scale, emphasisinstead being placed upon illustrating the principles of the invention.In the figures, like reference numerals designate corresponding partsthroughout the different views.

FIG. 1 is a block diagram of a video processing system.

FIG. 2 is a block diagram of a combined video processing system.

FIG. 3 is a detailed block diagram of the equalizer with integratedretimer.

FIG. 4 is block diagram of the equalizer as shown in FIG. 3 withdecision feedback equalizer.

FIG. 5 is block diagram of the equalizer as shown in FIG. 4 with astatus and performance monitoring module.

FIG. 6 is a signal plot of jitter verses cable length for a signalprocessed under the prior art and a signal processed by a combinedequalizer and jitter cleaner.

FIG. 7 illustrates an operational flow diagram of an exemplary method ofoperation.

DETAILED DESCRIPTION

The invention disclosed is an integrated equalizer & retiming elementwhich enables a lower power and lower cost solution, as compared to theprior art, for providing an integrated low jitter signal recoverysolution. By integrating the equalizing and retiming element, printedcircuit board (PCB) area requirements are reduced, and solution die areaand power consumption is also reduced. There is also a performancebenefit realized by avoiding the transmission of the equalized signalover a cable, bus or circuit board trace to get to the retiming element.

Due to random noise and inter symbolic interference (ISI), the pulse canshrink during transmission through a cable. When the post transmissionpulses go through a cross-point, backplane equalizer, etc, the pulsesbecome even narrower and can eventually vanish or appearindistinguishable. The smaller or vanished (indistinguishable) pulsescause bit errors. A jitter cleaner retimes all the pulses and makes themequal or have desired width of pulses. This ensured that signals can gothrough the bandwidth limited channels and be accurately recovered.

FIG. 1 is a block diagram of a video processing system. In thisembodiment, a signal is received over a cable 104, such as coax cable.In other embodiments other cables or paths may carry the signalincluding any metallic conductor, an optic channel, or a wireless path.The cable 104 connects to a connector 108. The connector 108 maycomprise any type connector configured couple a cable 104 to a printedcircuit board, integrated circuit, or any other element. In this exampleenvironment, the connector is a BNC connector.

The signal is then presented to an integrated circuit equalizer 112. Theequalizer performs equalization on the signal to adjust the magnitude ofthe signal at one or more frequencies to correct frequency specificattenuation of the signal as the signal passes through the cable 134.

On a separate integrated circuit in the prior art is the reclocker 120,which may also be referred to as a retimer or CDR (clock data recovery)circuit. After processing by the equalizer 112, the signal is presentedover one more separate channels on a printed circuit board or backplaneto the reclocker 120. The reclocker processes the signal and generates aduplicate signal which has jitter removed or reduced.

As a drawback to the system of FIG. 1, the equalizer 112 and thereclocker 120 are on separate integrated circuits. As a result there aretwo different and distinct integrated circuits. This adds additionalcost and additional space requires, both of which are limited in modernprinted circuit board design. If two integrated circuits are used theremust also be the two packages which adds additional cost and potentialfor failure. In addition, if two integrated circuits are used it isnecessary to electrically connect the equalizer integrated circuit withthe reclocker integrated circuit. To electrically connect eachintegrated circuit an electrically conductive path must be establishedfrom the integrated circuit, through the package, through the printedcircuit board, and then into the second package, and into the secondintegrated circuit. This path, which is typically closely located withother conductors carrying signals and electrically unshielded, resultsin unwanted cross talk and coupling. This reduces the maximum bit ratefor transmission or reduces the maximum cable length. Echo, reflectionand other unwanted signal effects may also be introduced into the videosignal.

FIG. 2 is a block diagram of a video processing system. In this exampleenvironment of use, a video signal is received from a remote location orfrom a source, such as a camera or other processing or video/imagegeneration unit. Equipment from which the signal may be received includebut are not limited to a switch, camera, monitor with pass through,amplifier, or any other element capable of transmitting or generating avideo signal.

As shown in this embodiment a coaxial cable 204 connects to a connector208, which in turn presents a signal to a combined equalizer and retime(jitter cleaner) 212. Although shown as a coax cable, any type channelmay carry the signals including twisted pair channel, traces on printedcircuit board, a backplane channel, a wireless channel, or any channelconfigured for long distance transmission of the signal such as over 75meters. In this embodiment, the cable is terminated with and connects tothe processing equipment with a BNC connector 208. In other embodiments,any other type connector may be used. The signal may operate at anySMPTE standard data rates including but not limited to 2.97 Gb/s, 1.485Gb/s, 5.94 Gb/s, or 11.88 Gb/s.

The signal may undergo processing before connecting to the equalizerwith an integrated retimer, such as with an analog front end (notshown), or connected directly to the combined equalizer and retime 212.The equalizer with retimer 212 (contained on a signal die and/or locatedwithin a single package) process the received signal to perform bothequalization and retiming within a single integrated circuit.

Integrating both systems into a single integrated circuit avoids theneed for separate discrete integrated circuits or separate circuitboards for each function. This in turn reduces cost and spacerequirements, and increase reliability due to a single package andassociated connections and traces. In particular, between two differentpackages, which comprise the outer housing that contains a die, innerdie having integrated circuits thereon, connection pins for conductingelectrical signal, and the bond wires which connect the pin to the die,the pins can be in short supply. The pins are important to carry signalsinto and out of the package and die. By forming both the adaptiveequalizer and the jitter cleaner on the same integrated circuit, therequired pin count can be reduced, or other signals may be carried onthe existing pins thereby increasing processing or monitoringcapability. In this situation, it is possible to reduce the pin countfor a driver pin and an input pin before the reclocking circuit (jittercleaner).

In addition, as discussed below in greater detail, the systemperformance is increased as compared to the prior art. In addition,power reduction is also improvied by having both elements in a singleintegrated circuit which allows for shared systems and reduced powerconsumption. As discussed below, additional benefits are also realized.

In one embodiment the adaptive equalizer and the jitter cleaner areelectrically isolated to reduce crosstalk or coupling between the signalbeing processed by each element. These devices are thus placed onislands within the die to establish desired isolation.

In this embodiment, the output of the equalizer with retimer 212 isprovided to a FPGA (field programmable gate array) 224, or otherprocessing element. In other embodiments the system may be configuredwithout the FPGA 224 and the output of the equalizer with retime 212 mayconnect directly to a switch 230, such as a crosspoint switch, or otherelement. In this embodiment the output of the processing system connectsto a switch card 234 configured as a cross point switch. In otherembodiments, the output may connect to processing elements in additionto or other than a crosspoint switch.

The signal presented to the equalizer with retimer contains phase jitterand other unwanted signal degradation, such as frequency specificattenuation due to passage through the channel. The signal output fromthe equalizer with retimer does not possess jitter and as a result thedifferences between each adjacent pulse may be clearly detected andidentified.

FIG. 3 is a block diagram of the equalizer with retimer 300 as shown inFIG. 2. This is but one possible block diagram and in other embodimentsother configurations may be arrived at by one of ordinary skill in theart. An input signal SDI 304 is provided to the combined equalizer withretimer. In this exemplary configuration the input comprises an SDI(serial digital interconnect) signal which is presented to an amplifier308 or gain element. The amplifier 308 increases the magnitude of thesignal for processing by the subsequent processing elements. The outputof the amplifier also connects to a multiplexer 324 as shown. An analogfront end (not shown) may also be part of one or more embodiments toperform processing in the analog domain, or the system described hereinmay be part of the analog front end (AFE).

The amplified signal is provided to an adaptive equalizer 312. Theadaptive equalizer 312 may comprise one or more filters or gain elementswhich are configured to selectively amplify, such as on a frequencyspecific basis, or attenuate the signal to account for frequencyspecific attenuation of the channel. The systems described hereininclude auto detection to automatically adjust for and operate withsignals of any bit rate.

The output of the adaptive equalizer 312 connects to a jitter cleaner316 and the multiplexer as shown. The jitter cleaner 316 comprises anydevice configured to reduce or eliminate jitter in an electrical oroptic signal. In one embodiment the jitter cleaner comprises or includesa clock data recovery (CDR) circuit, re-clocker which may include aphase lock loop, slicer, or any other device configured to reduce oreliminate jitter. The terms clock data recovery circuit, re-clocker, andjitter cleaner may be used interchangeably herein.

The output of the jitter cleaner 316 connects to the multiplexer 320. Asa result, in this embodiment the multiplexer 320 receives three inputs:the amplified signal, the adaptive equalizer 312 output, and the jittercleaner 316 output. Responsive to a control signal, the multiplexer 320may output any of these three signals on either of the two outputs.

In other embodiments the multiplexer 320 may not be included, or it mayonly output a single output to the driver. The control signal may begenerated from a processor or control logic that is within the equalizerwith retimer 300, or external to the equalizer with retimer 300. In oneembodiment the control signal to the multiplexer 320 is generated orreceived by the interface 330.

In the embodiment shown, having the multiplexer 320 with two outputs, afirst output connects to a driver 324. The driver 324 is configured toamplify and output the equalized and jitter cleaned signal at a powerlevel suitable for downstream processing or transmission on an output332. A second output connects to a digital interface 330, which providesan interface for a user or a secondary processing or diagnostic system.The digital interface 330, in connection with rest of the system, may beused to create a diagnostic signal, such as test patterns for channelanalysis, or to allow access to the system setting or system performanceparameters.

In one configuration, one or more of the three different signals inputto the multiplexer 320 may be processed for diagnostics purposes or toevaluate the channel, such as the cable. For example, the amplifiedsignal may be analyzed to determine the channel's transfer function orto determine the quality of the channel. Likewise, the amplified signalmay be compared to either of the equalized signal or the jitter cleanedsignal to determine the amount of jitter or attenuation by comparingthese signals.

It is also contemplated that if the amplified signal contains nominal ora moderate amount of jitter or frequency specific attenuation, theeither or both of the adaptive equalizer 312 and/or the jitter cleaner316 may be shut down or disabled to reduce power consumption. Forexample, if the signal was transmitted only a short distance, then thesignal may not require jitter removal, such as with a CDR system, and asa result, these processing blocks may be shut down to reduce powerconsumption. The multiplexer 320 may then output the signal having noequalization or no jitter correction. It is contemplated that in someembodiments the adaptive equalizer 312 may remain on at all times.

FIG. 4 illustrates a block diagram of a combined equalizer and jittercleaner with integrated decision feedback equalizer. This is but oneexample configuration of an adaptive equalizer and jitter cleaner thatalso includes a decision feedback equalizer (DFE). Other embodimentswith the DFE arranged at different locations in relation to the othercircuitry are possible. As compared to FIG. 3, common elements areidentified with identical reference numbers although such elements areadapted to operate in the configuration of FIG. 4.

As shown in FIG. 4, the adaptive equalizer 312 also includes or operatesin connection with a rate determination module 408. The ratedetermination module monitors the received signal and determines the bitrate, or other rate unit, for the incoming signal. In one embodiment thebit rate is calculated by detecting the number of rising of fallingedges during a predetermined time period. As discussed below in greaterdetail the bit rate may be used to control one or more other functions.In this configuration the rate determination module 408, which is partof the adaptive equalizer 312, receives a feedback signal from thejitter cleaner 316.

The output of the adaptive equalizer 312 feeds into a decision feedbackequalizer (DFE) 412. The DFE is a filter that uses feedback of detectedsymbols or signal levels, in addition to optional conventionalequalization of future symbols or signals. Some embodiments may usepredefined training sequences to provide reference points for theadaptation process of the DFE coefficients. DFE processing is known bythose of ordinary skill in the art and as a result is not discussed ingreat detail herein. The DFE also receives a feedback signal from thejitter cleaner 316 as shown. Using this feedback signal the coefficientswithin the DFE 412 may be accurately adapted and dynamically updatedduring operation to achieve optimal operation. The DFE 412 provides thebenefit of reducing or eliminating noise that coupled onto or otherwiseis corrupting the signal. This is in contrast to the adaptive equalizer312 which accounts for frequency specific attenuation to the signal inthe channel.

The output of the DFE is presented to the jitter cleaner 316 forprocessing as described above to generate a signal that is not onlyprocessed for frequency specific attenuation and noise but also jitterto establish a signal having a fully open signal eye.

In this embodiment the interface 330 may be in communication with one ormore of the adaptive equalizer 312, the DFE 412, jitter cleaner 316, andthe multiplexer 320. As described above, the interface 330 enable accessto one or more of these systems by a user or by other systems in thecommunication device.

FIG. 5 illustrates a block diagram of a combined equalizer and jittercleaner with integrated decision feedback equalizer. This is but oneexample configuration of an adaptive equalizer and jitter cleaner thatalso includes a decision feedback equalizer (DFE) and astatus/performance monitor with shared biasing. Other embodiments withthe status/performance monitor arranged at different locations inrelation to the other circuitry are possible. As compared to FIGS. 3 and4, common elements are identified with identical reference numberalthough such elements are adapted to operate in the configuration ofFIG. 5.

In this example embodiment a status/performance monitor 508 isconfigured to be in communication with or between the interface 330 andthe other components 312, 412, 316. The status/performance monitor 508is configured to monitor one more aspects of operation of the adaptiveequalizer 312, DFE 412, and jitter cleaner 316. The status andperformance monitor 508 may comprise control logic, processor, ASIC,FPGA, or any other device or system, with or without software,configured to perform as described herein.

In one embodiment the status/performance monitor 508 is configured tomonitor one or more aspects of operation and responsive thereto shutdown one or more elements of the system to reduce power consumption. Forexample, the rate determination module 408 determines the bit rate andthe status and performance monitor 508 may then compare the bit rate toa threshold value. The threshold value is a bit rate below which certaindevices may be turned off or disabled to reduce power consumption. Ifthe actual bit rate is below a threshold, the status and performancemonitor 508 can turn off the DFE 412, the jitter cleaner 316, or both.While the adaptive equalizer 312 may be maintained active, it iscontemplated that some aspects of the adaptive equalizer may be shutdown or reductions in processing may occur. In one embodiment thethreshold value is 1 gigabits per second. In other embodiment other bitspeeds may be selected for the threshold value. In one embodiment theadaptive equalizer may also be disabled to reduce power consumptionwhile in other embodiments the adaptive equalizer is active at alltimes.

In another embodiment, the bit rate signal or other signal informationis provided to the jitter cleaner 316 directly and the jitter cleanerdetermines whether to disable operations or processes the output fromthe adaptive equalizer 312. It is also contemplated that instead of amultiplexer or switch, the signal may be passed through the jittercleaner 316 directly without jitter cleaning processing, which may bedisabled based on the bit rate to reduce power consumption.Alternatively, the equalizer 312 could be configured to perform thedetecting of the bit rate, comparing to a threshold, and the disablingof the jitter cleaner 316. It is also contemplated that a feedback loopmay be implemented to monitor the bit rate and control operation of thejitter cleaner. It is also disclosed herein that differing degrees orlevels of jitter reduction may be implemented to only perform the amountof jitter reduction required to meet specification while also reducingpower consumption.

It is further contemplated that the status and performance monitor 508may serve as an automated controller or a user input based controller tomonitor one or more aspects of operation of the adaptive equalizer 312,DFE 412 and jitter cleaner 316 to coordinate and improve operation. Inone embodiment, the status and performance monitor 508 receives andprocesses input from the adaptive equalizer 312, DFE 412 and jittercleaner 316 to thereby control operation of one or more of these devicesof improve performance or reduce power consumption. The input to thestatus and performance monitor 508 may include coefficients, inputsignals, output signals, or any other setting or parameter. Bymonitoring and optionally adjusting one or more setting or aspect ofoperation of the adaptive equalizer 312, DFE 412 and jitter cleaner 316in a coordinated manner, improved performance and/or power savings maybe realized in a way not possible in the prior art.

The status and performance monitor 508 is also coupled to the interface330. This provides for user access to not only the adaptive equalizer312, DFE 412, and jitter cleaner 316 signals and settings, but also thesettings and data in the status and performance monitor 508. Thus, theuser can set the thresholds, settings, and system optimization routinesto be executed and set by the status and performance monitor 508.

Also shown in FIG. 5 is a shared bias circuit 512 having an output 516that connects to the elements of FIG. 5 that require biasing such as,but not limited to, one or more of the amplifier 308, equalizer 312, DFE412, jitter cleaner 316 and the driver 324. To reduce complexity adirect connection of the bias output 516 to each element is not shown inFIG. 5 however one or more outputs may be provided from the shared biascircuit 512 depending on the biasing requirements of the individualelements of FIG. 5. By having a shared bias circuit, power savings,space savings, and costs savings are realized over the prior art. Inprior art systems, two biasing systems were required for biasing theseparate integrated circuits, namely the adaptive equalizer IC and theseparate jitter cleaner IC, which increased cost, size, and powerconsumption.

In addition, the status monitor and/or the user interface may also beshared by both the adaptive equalizer 312 and the jitter cleaner 316. Byhaving both of these elements (adaptive equalizer and the jittercleaner) on a single integrated circuit, the system may utilize a sharedstatus and performance monitor and/or the user interface as compared toprior art systems which required two status and performance monitors andtwo user interfaces. This further reduces power consumption, spacerequirements, and cost.

FIG. 6 is a signal plot of jitter verses cable length for signalsprocessed under both the prior art system shown in FIG. 1 and a signalprocessed with the combined equalizer and jitter cleaner shown in FIG.2. The horizontal axis 604 represents cable length in meters while thevertical axis 608 represents output jitter. In this exemplary plot thesignal without the integrated jitter cleaning shows a marked increase inoutput jitter at cable lengths greater than one hundred meters. Incontrast, the signal which is equalized and jitter cleaned has agenerally constant and low jitter level across a wide range of cablelengths.

As shown, for signal plot 612 which undergoes processing by only theadaptive equalizer, the output jitter at cable lengths beyond 100 metersrises to unacceptable levels, particularly beyond 125 meters. As aresult, when jitter cleaner processing is added and the signal 620undergoes jitter reduction, the output jitter drops. However, even forlonger cable lengths, the jitter is undesirably high. The third signalplot 616 illustrates a signal that undergoes both adaptive equalizationand processing by the jitter cleaner when both the adaptive equalizerand jitter cleaner are both located on a single integrated circuit. Ascan be seen from signal plot 626, the resulting signal processingresults in a low jitter signal even at cable lengths up to 200 meters.This is a significant advantage over the prior art.

By implementing both the adaptive equalizer and the jitter cleaner onthe same integrated circuit the signal path does not require that thesignal from the adaptive equalizer pass out of the adaptive equalizerdie, through the package, through the circuit board, and then into thejitter cleaner package, bond wires and die. This path introduces signaldegradation and other unwanted affects, such as reflection, signal loss,and trace noise. By placing both the adaptive equalizer and jittercleaner on a single die in a single package, this prior art signaldegradation and the unwanted effects can be avoided.

FIG. 7 illustrates an operational flow diagram of an example method ofoperation. This is but one possible method of operation and as such,other methods of operation are possible that do not depart from thescope of the invention as described and claimed herein.

As shown in FIG. 7A, the operation starts at a step 704 by receiving asignal from the cable and amplifying the received signal to a magnitudesuitable for subsequent processing. Additional processing may occur suchas in an analog front end. At a step 708 the system performs adaptiveequalization on the signal to modify the signal for frequency specificattenuation that occurred as a result of the signal passing through thecable, which may be referred to herein as the channel. As is understood,different channels attenuate certain signal frequencies more that othersignal frequencies. The length of the channel also affects the level ofattenuation.

At a step 712 the rate determination module, or rate detector,calculates the bit rate, signal rate or frequency value. This may occurby monitoring peaks, transitions, rising edges, or falling edges of thereceived signal in relation to a known timer period. The rate, such asbit rate, of the received signal is provided to the status monitor oruser interface.

At step 712, the noise level (such as SNR) of the received signal mayalso be detected by the equalizer, rate detector, or other element andthis nose information may be provided to the status monitor.

Continually or periodically, the status monitor compares the signalnoise to a noise threshold. This occurs at a step 716. The noisethreshold is one or more values that define noise levels to which theactual noise value is compared. If the actual noise level is above thethreshold, then the operation advances to a step 728 for processing bythe DFE to reduce noise. If the noise level is below the noisethreshold, then the operation advances to step 724.

At step 724 the system, such as the status monitor or interface, mayoptionally disable the DFE to reduce power consumption and reduce heatgeneration. This may also increase system operation speed. Because thenoise level is below the threshold, the signal noise is acceptably lowand there is no need for processing of the signal by the DFE. It iscontemplated that the user or system may change the noise threshold, ora different noise threshold may be established for different bit ratesor other operating factors.

Alternatively, if the actual noise is not below the threshold noiselevel, then the operation advances to step 728. At step 728 the DFEprocesses the signal from the adaptive equalizer to remove or reducenoise that is part of the signal. In other embodiments, processing otherthan or in addition to processing by a DFE may occur. Instead of or inaddition to a DFE, other devices such as a multiple tap feed forwardequalizer may be part of the system.

At a step 732 the system compares the actual bit rate to a bit ratethreshold to determine if the actual bit rate is below the threshold.The bit rate threshold is a value at which the processing may beincreased or decreased to reduce power consumption. If the actual bitrate is below the bit rate threshold, then it is contemplated that thebit rate is slow enough that processing may be reduced without effectingsignal processing or increasing the bit error rate or signal detection.It is contemplated that the comparison may occur in the status monitor,the interface, or the adaptive equalizer.

If at decision step 736 the actual bit rate is below the bit ratethreshold, then the operation advances to a step 740 and the system,such as the status monitor or interface, disables the jitter cleaner.This reduces power consumption and heat generation. Because the bit rateis low, the processes of the jitter cleaner may not be required. In thissituation the signal may be routed through the jitter cleaner, butwithout processing, or the multiplexer may be controlled to output thesame signal that is presented as the input to the jitter cleaner,thereby bypassing the jitter cleaner.

Alternatively, if at step 736 the status monitor or interface determinesthat the actual bit rate is above the bit rate threshold, then theoperation advances to a step 744 and the signal is presented to anoperational jitter cleaner, i.e. jitter reduction is performed. Thejitter cleaner processes the signal to reduce or remove jitter.

Turning to FIG. 7B, the output of the jitter cleaner is evaluated by thestatus monitor or the interface to evaluate the signal quality output bythe jitter cleaner, such as but not limited to the signal eye, todetermine if the settings and parameters meet specification or ifadjustments to one or more aspects of the adaptive equalizer, DFE, orjitter cleaner should be made to improve one or more aspects of thesignal quality. These adjustments include but are not limited to a biastowards over or under equalization, amount of DFE, precursor correctionof multiple tap feed forward equalizer.

At a step 752, the jitter cleaner outputs the processed signal to amultiplexer, or optionally to other device such as a switch or an outputpin from the integrated circuit on which the adaptive equalizer and thejitter cleaner are both located. At a step 756 the multiplexer receivesa control signal from the status monitor, or other control logic orother controller. The control signal defines which input signal themultiplexer will present as its output. As discussed above, depending onthe noise and jitter associated with the signal, the multiplexer maypresent different input signals as the output.

At a step 760 the multiplexer, responsive to the control signal, outputsthe selected input signal as the output from the multiplexer. At step764 the signal from the multiplexer is presented to a driver foramplification and then presented on an output of the integrated circuit.

Other systems, methods, features and advantages of the invention will beor will become apparent to one with skill in the art upon examination ofthe following figures and detailed description. It is intended that allsuch additional systems, methods, features and advantages be includedwithin this description, be within the scope of the invention, and beprotected by the accompanying claims. While various embodiments of theinvention have been described, it will be apparent to those of ordinaryskill in the art that many more embodiments and implementations arepossible that are within the scope of this invention. In addition, thevarious features, elements, and embodiments described herein may beclaimed or combined in any combination or arrangement.

What is claimed is:
 1. An integrated system for adaptive equalizationand jitter reduction comprising: an input configured to receive a videosignal from a channel; an adaptive equalizer configured to applyfrequency specific signal modification to the received signal to presentan equalized signal on an adaptive equalizer output; a bit rate detectorconfigure to determine a detected bit rate of the video signal or theequalized signal; a jitter cleaner having a jitter cleaner input coupledto the adaptive equalizer output, the jitter cleaner configured toprocess the equalized signal to reduce jitter in the equalized signal tocreate a jitter cleaner output; a multiplexer configured to receive theequalized signal and the jitter cleaner output and, responsive to acontrol signal, output either the equalized signal or the jitter cleaneroutput; a status monitor configured to: compare the detected bit rate toa bit rate threshold; responsive to the detected bit rate being greaterthan the bit rate threshold, activate the jitter cleaner to processesthe equalized signal and generate a control signal which causes themultiplexer to output the jitter cleaner output; and responsive to thedetected bit rate being greater than the bit rate threshold, activatethe jitter cleaner to processes the equalized signal and generate acontrol signal which causes the multiplexer to output the jitter cleaneroutput.
 2. The system of claim 1 further comprising an amplifierconfigured to amplify the signal prior to equalization by the adaptiveequalizer.
 3. The system of claim 1 wherein the jitter cleaner comprisesa clock and data recovery system.
 4. The system of claim 1 wherein thethreshold bit rate is 1 Gb/s.
 5. The system of claim 1 wherein thechannel is a coaxial cable having losses in excess of 30 dB at 1.5 GHz.6. The system of claim 1 wherein the signal is at SMPTE standard datarates including 5.94 Gb/s, 2.97 Gb/s and 1.485 Gb/s.
 7. The system ofclaim 1 further comprising a decision feedback equalizer located betweenthe adaptive equalizer and the jitter cleaner, the decision feedbackequalizer configured to process the equalized signal to reduce noise inthe equalized signal.
 8. The system of claim 7 further comprising anoise detector configured to compare noise on the video signal or theequalizer output to a noise threshold and responsive to the comparing,activate or disable the decision feedback equalizer.
 9. A combinedintegrated circuit configured as an equalizer and clock/data recoverysystem contained within a single package comprising: a packageconfigured with an inner area and two or more electrical pins; a dielocated in the inner area of the package and electrically connected tothe pins of the package, the die configured as an integrated circuitconfigured with the following elements: an equalizer configure toperform equalization of a received signal to generate an equalizedsignal; a clock/data recovery system configured to retime the equalizedsignal to create a retimed signal; a bit rate detector configured tocalculate a bit rate of the received signal; a comparator configured tocompare the bit rate of the received signal to a bit rate threshold; anda control circuit configured to selectively power down the clock/datarecovery system if the bit rate of the received signal is below the bitrate threshold.
 10. The system of claim 9 wherein the die furtherincludes a decision feedback equalizer configured to receive and processthe equalized signal and present a decision feedback equalizer processedsignal to the clock data recovery system.
 11. The system of claim 10wherein the control circuit is further configured to power down thedecision feedback equalizer based on one or more parameters of thereceived signal.
 12. The system of claim 9 further comprising a switchconfigured to receive the equalized signal and the retimed signal and ifthe clock/data recovery system is powered down, then output theequalized signal and if the clock/data recovery system is not powereddown, then output the retimed signal.
 13. The system of claim 9 whereinthe control circuit is part of a status monitor, the status monitor isconfigured to process the bit rate and generate the control signal. 14.The system of claim 9 further comprising a status monitor with interfaceto access one or more parameters of the equalizer and clock/datarecovery system and monitor the equalized signal and retimed signal. 15.A method for processing a video signal to perform noise and jitterreduction, the method comprising: receiving a video signal; performingadaptive equalization on the video signal with an adaptive equalizer tocreate an equalized signal; providing the equalized signal to a switchand a retiming circuit; comparing one or more aspects of the equalizedsignal to a threshold; responsive to the comparing, either outputtingthe equalized signal or activating a retiming circuit to process theequalized signal to create and output a retimed signal.
 16. The methodof claim 15 wherein the retime circuit comprises a clock/data recoverycircuit including a phase lock loop circuit.
 17. The method of claim 15further comprising performing processing with a decision feedbackequalizer to reduce noise on at least one of the video signal, theequalized signal, or the retimed signal.
 18. The method of claim 15wherein the performing adaptive equalization and processing theequalized signal to create a retimed signal occurs within the sameintegrated circuit.
 19. The method of claim 15 further comprisinggenerating a control signal which is presented to a switch to controlwhich input to the switch is output from the switch, such that theswitch input includes at least the equalized signal and the retimedsignal.
 20. The method of claim 15 further comprising coupling theadaptive equalizer and retiming circuit to a user interface or statusmonitor.
 21. The method of claim 15 wherein the one or more aspects ofthe equalized signal is a bit rate of the equalized signal or the videosignal and a bit rate detector determines the bit rate.